1. Field of the Invention
The present invention relates to a hetero bipolar transistor and a method of manufacturing the same, particularly, to a hetero bipolar transistor which can be operated with a higher speed and a method of manufacturing the same.
2. Description of the Related Art
Miniaturization and improvement in the operating speed of a silicon bipolar transistor have now been achieved to some extent. Also, vigorous researches are being made nowadays on a silicon-based hetero bipolar transistor in an attempt to further improve the amplification factor and decrease the base resistance of the bipolar transistor.
FIG. 1 shows a first example of a conventional hetero bipolar transistor of so-called "mesa-type", which is a typical conventional silicon-based hetero bipolar transistor. As seen from the drawing, an N.sup.- -type silicon layer (collector region) 11, a P-type Si-Ge layer (base region) 12, and an N-type silicon layer (emitter region) 13 are successively formed by an epitaxial growth method on an N.sup.+ -type silicon substrate 10, followed by forming a P.sup.+ -type base contact region 14 by means of an ion implantation. Then, the laminate structure consisting of these epitaxial layers is selectively removed by etching to form a mesa structure including the P.sup.+ -type base contact region 14, followed by forming an insulating film 15 covering the entire surface including the side wall of the mesa structure. After formation of the insulating film 15, emitter and base openings are formed, followed by forming an emitter electrode 18 and a base electrode 17. Further, a collector electrode 16 is formed on the back surface of the substrate.
The conventional hetero bipolar transistor in FIG. 1 has a rough surface and, thus, is unsuitable for forming an integrated circuit. It should also be noted that the P.sup.+ -type base contact region 14 is formed after formation of the epitaxial layers in the first prior art shown in FIG. 1. What should be noted is that the heat resistance of the Si-Ge layer 12 included in the epitaxial layers is relatively low. Specifically, the Si-Ge layer 12 is capable of resisting heat of only about 850.degree. C., with the result that a sufficient heat treatment cannot be applied to the P.sup.+ -type base contact region 14 after the ion implantation step. It follows that the base resistance cannot be lowered sufficiently. What should also be noted is that pn junctions are formed between the P.sup.+ -type base contact region 14 and the emitter region 13 and between the region 14 and the collector region 11, leading to an increased emitter-base capacitance and an increased base-collector capacitance.
FIG. 2 shows a second example of a conventional hetero bipolar transistor, which is a typical example of a conventional bipolar transistor of a non-self-alignment type. The second prior art shown in FIG. 2 is of a planar type. As shown in the drawing, an N.sup.+ -type silicon buried layer 21 and an N-type silicon layer (collector region) 22 are formed in this order on a P-type silicon substrate 20, followed by forming an element separation region 23 consisting of an insulating material so as to define an element-forming region. In the next step, a P-type Si-Ge layer 24 is formed in a manner to cover a transistor-forming region. That portion of the Si-Ge layer which is in contact with a silicon single crystal forms a single crystalline Si-Ge layer 24a. On the other hand, that portion of the Si-Ge layer which is in contact with the element separating region 23 forms a polycrystalline Si-Ge layer 24b.
Further, an etching-stopping layer (SiN layer) 25 is formed in a manner to cover an emitter-forming region on the surface of the single crystalline Si-Ge layer (base region) 24a. After formation of the etching-stopping layer 25, a P.sup.+ -type polycrystalline silicon layer 26 acting as a lead wire connected to the base region is formed in a manner to cover the etching-stopping layer 25 and the Si-Ge layer 24. Then, that portion of the P.sup.+ -type polycrystalline silicon layer 26 which is positioned in the emitter-forming region is removed, followed by forming an insulating layer 27 in a manner to cover the P.sup.+ -type polycrystalline silicon layer 26. Further, the etching-stopping layer 25 positioned within the emitter-forming region is removed, followed by forming an emitter polycrystalline silicon layer 28. Finally, a collector electrode 16, a base electrode 17, and an emitter electrode 18 are formed as shown in the drawing.
The second prior art shown in FIG. 2 is of a planar type, making it possible to use the second prior art for forming an integrated circuit. In this prior art, however, the P.sup.+ -type polycrystalline silicon layer leading to the base region is not self-aligned with the base layer, with the result that the base resistance is increased. Further, openings are formed in the etching-stopping layer 25 before formation of the emitter polycrystalline silicon layer 28. What should be noted is that the surface of the single crystalline Si-Ge layer is exposed to the outer atmosphere when the openings are formed in the etching-stopping layer, with the result that a natural oxide film is formed on the exposed surface. It follows that it is difficult to control the interface between the emitter polycrystalline silicon layer 28 and the base Si-Ge layer 24a.
FIG. 3 shows a third example of a conventional hetero bipolar transistor, which is of a typical self-alignment type. As shown in the drawing, an N.sup.+ -type silicon buried layer 31 and an N-type silicon layer (collector region) 32 are formed in this order on a P-type silicon substrate 30, followed by forming an element separating region 33 consisting of an insulating material so as to define an element-forming region. Then, a second insulating film 34 is deposited on the substrate surface, followed by forming a P.sup.+ -type polycrystalline silicon layer 35 acting as a wiring leading to a base region and subsequently forming an insulating film 36 in a manner to cover the upper and side surfaces of the polycrystalline silicon layer 35. Further, the insulating film 36 and the P.sup.+ -type polycrystalline silicon layer 35 on an emitter-forming region are selectively removed to selectively expose the second insulating film 34, followed by forming a first side wall 37 consisting of an insulating film. In the next step, the exposed portion of the second insulating film 34 is removed by etching to form an opening. In this step, the opening extends sideward because of the side etching of the second insulating film 34. After the etching step, a P-type Si-Ge epitaxial layer (base region) 38 is formed within the opening thus formed. Then, the opening above the base region 38 is filled with an insulating film, followed by selectively etching the insulating film. In this step, a second side wall 39 is formed because of the side etching effect. Further, an emitter polycrystalline silicon layer 19 is formed in the opening resulting from the selective etching of the insulating film. Still further, the insulating films covering the collector region, base region and emitter region are selectively removed to form openings, followed by forming a collector electrode 16, a base electrode 17 and an emitter electrode 18 in the openings thus formed.
In the third prior art shown in FIG. 3, the insulating film filling the opening positioned above the base Si-Ge layer 38 is removed by an reactive ion etching (RIE) to form the second side wall 39. What should be noted is that the thin base Si-Ge layer 38 is struck by ions during the reactive ion etching step. As a result, problems take place such as reduction in the thickness, contamination and disturbance of crystals of the base Se-Ge layer 38, leading to difficulties in the control capability and element characteristics of the device. Also, the Si-Ge base layer 38 is exposed to the outside before formation of the emitter polycrystalline silicon layer 19, as in the second prior art shown in FIG. 2. As a result, a natural oxide film is formed, making it difficult to control the interface between the emitter polycrystalline silicon layer 35 and the base Si-Ge layer 38.
As described above, the conventional hetero bipolar transistors leave much room further improvements. To reiterate, the first prior art shown in FIG. 1, i.e., a hetero bipolar transistor of mesa type, is not suitable for forming an integrated circuit. Also, the first prior art has a high base resistance and a high parasitic capacitance between the emitter and base regions and between the base and collector regions. When it comes to the second prior art shown in FIG. 2, i.e., a hetero bipolar transistor of a planar non-self-alignment type, it is certainly possible to use the bipolar transistor forming an integrated circuit. However, the second prior art has a high base resistance because the transistor is of a non-self-alignment type. Also, since the surface of the base Si-Ge layer is exposed to the outside before the step of forming the emitter layer, the exposed surface of the base layer tends to be contaminated, making it difficult to control as desired the interface between the base and emitter regions.
The third prior art shown in FIG. 3, i.e., a hetero bipolar transistor of a planar and self-alignment type, certainly permits improving the problems inherent in the first and second prior arts to some extent. In the third prior art, however, it is necessary to form the second side wall because the transistor is of a self-alignment type. What should be noted is that the second side wall is formed by selectively removing an insulating film formed in advance. The insulating film is selectively removed by a reactive ion etching. During the reactive ion etching step, a thin base Si-Ge layer is struck by ions. As a result, mechanical damages are done to the base Si-Ge layer such as reduction in the thickness, contamination and crystal disturbance, leading to difficulties in the control capability and element characteristics. Further, the surface of the base Si-Ge layer is exposed to the air atmosphere during the manufacturing process of the hetero bipolar transistor, as in the second prior art shown in FIG. 2. It follows that the surface of the base Si-Ge layer tends to be contaminated. Also, it is difficult to control the interface between the emitter and base regions.